1. Field of Invention
The present invention relates to Integrated Circuits (ICs) and more particularly to testing ICs with power-shutoff features.
2. Description of Related Art
The use of scan chains greatly simplifies the chip testing process for Application Specific Integrated Circuits (ASICs). Automatic test pattern generation (ATPG) techniques can assume each sequential element of the chip can be controlled as well as observed. Typically the ATPG system generates a number of test patterns and test responses. The test patterns are loaded into the chip through the scan chains, the test is executed, typically by running the chip through one or more clock cycles, and the resulting response is scanned out and compared to the expected good response. When there is a mismatch, the chip is identified as faulty, and if needed the mismatches from one or more patterns can be analyzed to determine the likely location of the failure on the chip.
However, scan testing is a power intensive process. In many cases the test pattern and the response data is very similar to random 0's and 1's, causing close to 50% of sequential elements in the design to change state during each shift of the scan load and unload process (the scan pattern for the next test can be loaded at the same time the response from the previous test is unloaded). This percentage is much greater than that typically found during normal chip operation. The percentage of the chip's logic that toggles while executing the test is also much higher than what is seen during normal functional operation. If the power aspects of scan testing are not addressed, it's possible that good chips will fail the testing process due to power droop caused by scan test's excessive power requirements. This effectively increasing the chip's manufacturing cost.
As a result, issues related to power consumption during manufacturing scan testing have been examined in some contexts. In the past, it was often possible to reduce average power consumption by reducing the scan speed, albeit at the expense of longer test time and increased test cost. However, today's scan load/unload clock frequency is typically much slower than the system clock frequency, and power consumption from timed delay or at-speed tests as well as instantaneous switching power during scan shifting has become an issue. (In general, instantaneous switching power is the power consumed by an individual clock pulse and cannot be reduced by lowering the scan shift clock frequency.) The problem in these cases is that the clock events trigger enough switching activity in the circuit that voltage droop occurs and parts of the circuit operate incorrectly. When this occurs during scan shifting, power problems appear to manifest themselves as one or more broken scan chains. During timed tests or during the capture of the test response, power problems appear as false failures.
Several techniques have been proposed to address the power issues that result from excessive switching activity. Some have tackled the problem during the generation of the test vectors through modification of the ATPG algorithm. Others have proposed a reordering of the scan cells and data vectors based on an previously generated set of ATPG vectors. Test vector ordering is another approach which is shown to reduce power consumption by as much as 50%. Special vector compaction and data compression is also shown effective at reducing power. Finally, clock modification schemes can also be used. Because many of these techniques tackle the power consumption problem in different ways, many of these techniques can be used together to reduce power consumption even further.
Many modern system-on-chip designs incorporate sophisticated techniques to control power requirements during functional operation. One such technique, known as power shut-off, allows an unused sub-component of the chip to power off while other parts of the chip remain operative. Power shut-off capabilities offer new challenges during manufacturing test, but also present unique opportunities. Performing scan testing while also shutting off power to certain parts of the chip would not only reduce the average power requirement, but would also address the power problems associated with delay testing and instantaneous switching. In addition, allowing parts of the chip to be shut-off allows testing under conditions that more closely match those encountered during functional operation. However, conventional scan testing designs and methods do not typically incorporate power-shutoff aware features.
Thus, there is a need for systems and methods that incorporate scan testing with power-shutoff aware features for ICs.